A typical wireless communication receiver includes a downconverter stage to translate a received radio frequency carrier signal to an intermediate frequency (IF) signal and thereafter (or direct) to a baseband signal. Many current wireless communication systems employ digital technology, which introduces complexity into the receiver's downconverter stage, whereby an input radio frequency signal is divided and multiplied by a local oscillator signal and a quadrature version of the local oscillator signal. The resulting outputs are known as the in-phase (I) and quadrature (Q) components. Filtering and amplification in the analogue stages typically precede analogue to digital conversion and subsequent filtering and amplification in the digital domain.
Imperfections within the analog components of the downconverter stage, or component differences between respective quadrature paths of the downconverter stage, can result in imbalances between the two branches, with respect to the relative amplitudes, relative phases, or both. These are known as IQ imbalances, and can have significant impact on the performance of a wireless receiver. Notably, the impact becomes more acute as higher-order modulation schemes or higher IQ bandwidth is employed. This is particularly true in the direct-conversion zero-IF receivers that are contemplated for many future orthogonal frequency division multiplex (OFDM) applications. Similar IQ imbalances can occur in the transmitter.
Most radio architectures that use digital modulation schemes require two digital to analog converters (DACs) in the transmit path to convert respective quadrature (I and Q) signals, and two analog to digital converters (ADCs) in the receive path to convert respective quadrature (I and Q) signals. An imbalance may occur between the ‘I’ and ‘Q’ paths. Another source of imbalance results from a residual delay error existing between clock edges used in each corresponding component or circuit (i.e. the ADC ‘I’ and the ADC ‘Q’ or the DAC ‘I’ and the DAC ‘Q’). This residual delay error is dependent on the circuit layout and silicon process used and leads to a resultant sampling error between the circuits and components.
An additional recent development in wireless communications has introduced further short or intermediate range wireless capabilities to wireless communication units, e.g. WiFi™. One problem resulting from the introduction of WiFi™ to current wireless communication units (as reported in 802.11n/ac/ad/ah standards) is the requirement to support improved signal-to-noise ratios (SNRs), over an increased bandwidth, which exacerbates the need to maintain tight control of IQ imbalances. The inventor of the present invention has also recognised that subcarriers on the edges of the spectrum employed by such wireless communication units are particularly sensitive to sampling errors when estimating IQ imbalance, which limits the transmit error vector magnitude (TX EVM) in transmit circuitry, or results in poor accuracy in receiver demodulation circuitry.
Previous attempts to correct for these IQ imbalances have relied on adaptive statistical estimation techniques, wherein a reference signal is constructed, using estimates of the effects of the IQ imbalance, and compared to the actual received signal in order to generate an error signal. The error signal is adaptively reduced in order to refine the estimates of the statistics relating to the IQ imbalance, see, for example, U.S. Patent Application Publication US 2006/0029150. This approach is computationally complex, however, and may not be robust enough for all situations. For example, convergence rates may be unacceptably slow. US 20120328041 A1 proposes using a loop back technique for image estimation, albeit that the result will produce a phase imbalance estimate due to the effect of synthesizers.